View KS8993I_586005.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KS8993
Micrel
KS8993
3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.05
General Description
The KS8993 contains three 10/100 physical layer transceivers, three MAC (Media Access Control) units with an integrated layer 2 switch. The device runs in two modes. The first mode is a three port integrated switch and the second is as a three port switch with the third port decoupled from the physical port. In this mode access to the third MAC is provided using a reverse or forward MII (Media Independent Interface) such that an external MAC can be directly connected to the KS8993. This interface also supports the 7-wire (serial network interface) as used by some routing devices. Useful configurations include a stand alone three port switch as well as a two port switch with a routing element connected to the extra MII port. The additional port is also useful for public network interfacing.
The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping at system reset time. On the media side, the KS8993 supports 10BaseT, 100BaseTX and 100BaseFX as specified by the IEEE 802.3 committee. Physical signal transmission and reception are enhanced through use of analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com.
Functional Diagram
Look-Up Engine (1K Entries) SRAM Buffers (16Kx32)
Queue Management
Buffer Management
FIFO and Flow Control
MAC 1
MAC 2
MAC 3
M I I MII / SNI (exclusive) External Interface
MRXD[3:0] MRXDV MCOL MCRS MRXCLK MTXD[3:0] MTXEN MTXER MTXCLK MCOLIN MRXD[0] MRXDV MCOL MRXCLK MTXD[0] MTXEN MTXCLK
Physical Transceiver 1
RXP[1], RXM[1]
Physical Transceiver 2
RXP[2], RXM[2]
Physical Transceiver 3
RXP[3], RXM[3]
S N I
TXP[1], TXM[1]
TXP[2], TXM[2]
TXP[3], TXM[3]
LED and Programming Interface
LED[1][3:0] LED[2][3:0] LED[3][3:0]
Micrel, Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
May 2005
1
KS8993
KS8993
Micrel
Features
* 3-port 10/100 integrated switch with physical layer transceivers * 64k Byte of SRAM on chip for frame buffering * 1.0Gbps high performance memory bandwidth * 10BaseT, 100BaseTX and 100BaseFX modes of operation * Support for UTP or fiber installations * Superior analog technology for reduced power and die size * Supports port based VLAN * QoS feature!! Supports 802.1p based priority or portbased priority * Indicators for link, activity, full/half-duplex and speed * Unmanaged operation via strapping at system reset time * Hardware based 10/100, full/half, flow control and autonegotiation * Individual port forced modes (full-duplex, 100BaseTX) when auto-negotiation is disabled * Wire speed reception and transmission * On chip integrated address look-up engine, supports 1K absolute MAC addresses * Automatic address learning, address aging and address migration * Full-duplex IEEE 802.3x flow control (Pause) with force mode option * Half-duplex back pressure flow control * Comprehensive LED support * External MAC interface (MII or SNI 7-wire ) for router applications * 300mA (0.75W) including physical transmit drivers * Commercial temperature range: 0C to +70C * Industrial temperature range: -40C to +85C * Available in 128-pin PQFP with single 2.5V power supply
Ordering Information
Part Number Standard KS8993 KS8993I Pb-Free KSZ8993 - Temperature Range 0C to +70C -40C to +85C Package 128-Pin PQFP 128-Pin PQFP
KS8993
2
May 2005
KS8993
Micrel
Revision History
Revision 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 1.14 1.15 1.16 2.00 Date 04/13/00 05/31/00 06/08/00 09/20/00 10/30/00 10/31/00 11/08/00 12/21/00 03/23/01 03/26/01 04/19/01 04/20/01 05/10/01 06/08/01 06/26/01 08/1/01 08/9/01 4/8/02 Summary of Changes Document origination Miscellaneous changes Index repair MII forward correction. MRXD[3:1] correction. Update voltage ratings. Correct I/O descriptions. Correct mode operation for LED[1:3][0] Add timing information Correct pin information Correct VLAN description. Update MODESEL descriptions for packet size extensions Update electrical characteristics; Correct I/O information. Correct timing information Update I/O descriptions Define control for LED[3][3] Revise definition for LED[3][3] Update timing information and power dissipation Add power up timing description; Correct DISAN3 default mode. Correct LED [1] [1] to float configuration Add Reverse and Forward MII timing Correct reserve buffer from 128 to 96 for PRSV pin. Add max. current. Add force flow control Option as follows: Change pin 50 from reserved to FFLOW1# for force flow control on port 1.) Change pin 46 from reserved to FFLOW2# for force flow control on port 2. Modify LED[1][2] for force flow control on port 3. Add TX Disable for Port 1 and port 2, Power down for port 3 and Far end Fault Disable features using MUX[1:2] and TEST[1:2] pins. Recommend pull-down on LED[3][3] Convert to new format. Added reset circuit recommendation. Added lead-free part number
2.01 2.02 2.03 2.04 2.05
5/6/02 7/2/02 8/29/03 1/24/05 5/12/05
May 2005
3
KS8993
KS8993
Micrel
Table of Contents
System Level Applications .............................................................................................................................................................. 5 Pin Description I/O Grouping .............................................................................................................................................................................. 6 .............................................................................................................................................................................. 9
I/O Descriptions ............................................................................................................................................................................ 10 Pin Configuration ........................................................................................................................................................................... 15 Functional Overview: Physical Layer Transceiver ..................................................................................................................... 16 100BaseTX Transmit ............................................................................................................................................................... 16 100BaseTX Receive ................................................................................................................................................................ 16 PLL Clock Synthesizer ............................................................................................................................................................ 16 Scrambler/De-scrambler (100BaseTX only) ............................................................................................................................ 16 100BaseFX operation .............................................................................................................................................................. 16 100BaseFX Signal Detection ................................................................................................................................................... 16 100BaseFX Far End Fault ....................................................................................................................................................... 16 10BaseT Transmit ................................................................................................................................................................... 16 10BaseT Receive .................................................................................................................................................................... 16 Power Management ................................................................................................................................................................ 17 LED Mode Selection ................................................................................................................................................................ 17 Auto-Negotiation ...................................................................................................................................................................... 17 Functional Overview: Switch Core ............................................................................................................................................... 18 Address Look Up ..................................................................................................................................................................... 18 Learning .......................................................................................................................................................................... 18 Migration ......................................................................................................................................................................... 18 Aging ............................................................................................................................................................................ 18 Forwarding ...................................................................................................................................................................... 18 Switching Engine ..................................................................................................................................................................... 18 MAC (Media Access Controller) Operation ............................................................................................................................. 18 Inter Packet Group .......................................................................................................................................................... 18 Back off Algorithm ........................................................................................................................................................... 18 Late Collision .................................................................................................................................................................. 18 Illegal Frame ................................................................................................................................................................... 18 Flow Control .................................................................................................................................................................... 18 Full-Duplex Flow Control ................................................................................................................................................. 18 Half-Duplex Back Pressure ............................................................................................................................................. 18 VLAN Support .......................................................................................................................................................................... 19 QoS Priority Support ................................................................................................................................................................ 20 MII Interface Operation .................................................................................................................................................................. 21 SNI Interface (7-wire) Operation ................................................................................................................................................... 22 Absolute Maximum Ratings .......................................................................................................................................................... 23 Operating Ratings .......................................................................................................................................................................... 23 Electrical Characteristics .............................................................................................................................................................. 23 Timing Diagrams ............................................................................................................................................................................ 24 Reference Circuit ........................................................................................................................................................................... 29 4B/5B Coding MLT Coding ............................................................................................................................................................................ 31 ............................................................................................................................................................................ 32
802.1q VLAN and 802.1p Priority Frame ...................................................................................................................................... 33 Selection of Isolation Transformers ............................................................................................................................................. 34 Selection of Reference Crystals ................................................................................................................................................... 34 Package Outline and Dimensions ................................................................................................................................................ 35
KS8993
4
May 2005
KS8993
Micrel
public network access. The major benefits of using the KS8993 are the lower power consumption, unmanaged operation, flexible configuration and built in frame buffering. Two such applications are depicted below.
System Level Applications
The KS8993 can be configured to fit either in a three port 10/ 100 application or as a two port 10/100 network interface with an extra MII or SNI port. This MII/SNI port can be connected to an external processor and used for routing purposes or
Public Network Access
Routing Engine
KS8993 3-Port Switch with PHY
KS8993 3-Port Switch with PHY
3X Transformer or Fiber Interface 3-Port Stand Alone
2X Transformer or Fiber Interface
Or
2-Port with Public Network Interface
Figure 1. KS8993 Applications
May 2005
5
KS8993
KS8993
Micrel
Type(Note 1) GND I I GND I I Pwr O O O GND Pwr Pwr O GND GND Pwr GND I I Pwr O O O GND Pwr Pwr GND O O O Pwr I I GND I I GND 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 2 3 1 1 1 1 1 1 1 1 1
Pin Description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Note 1.
Pin Name GND_ANA MUX[2] MUX[1] GND_RX[1] RXP[1] RXM[1] VDD_RX[1] VREF[1] TXP[1] TXM[1] GND_TX[1] VDD_TX[1] VDD_BG ISET GND_BG GND_PLL VDD_PLL GND_RX[2] RXP[2] RXM[2] VDD_RX[2] VREF[2] TXP[2] TXM[2] GND_TX[2] VDD_TX[2] VDD_TX[3] GND_TX[3] TXP[3] TXM[3] VREF[3] VDD_RX[3] RXP[3] RXM[3] GND_RX[3] FXSD[2] FXSD[3] GND_ANA
Port
Pin Function Analog ground Factory test pin Factory test pin Ground for receiver Physical receive signal + (differential) Physical receive signal - (differential) 2.5V for receiver Reference voltage for transmit transformer center tap Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry 2.5V for transmit circuitry 2.5V for analog circuitry Set physical transmit output current Ground for analog circuitry Ground for phase locked loop circuitry 2.5V for phase locked loop circuitry Ground for receiver Physical receive signal + (differential) Physical receive signal - (differential) 2.5V for receiver Reference voltage for transmit transformer center tap Physical transmit signal + (differential) Physical transmit signal - (differential) Ground for transmit circuitry 2.5V for transmit circuitry 2.5V for transmit circuitry Ground for transmit circuitry Physical transmit signal + (differential) Physical transmit signal - (differential) Reference voltage for transmit transformer center tap 2.5V for receiver Physical receive signal + (differential) Physical receive signal - (differential) Ground for receiver Fiber signal detect Fiber signal detect Analog ground
Pwr = power supply GND = ground I = input O = output I/O = bi-directional
KS8993
6
May 2005
KS8993
Pin Number 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
Note 1.
Micrel
Pin Name TEST[1] TEST[2] GND_RCV[2] VDD_RCV[2] GND_RCV[3] VDD_RCV[3] VMDIS FFLOW2# PV32 PV31 PV23 FFLOW1# PV21 PV13 PV12 DISAN3 VDD GND MTXEN MTXD[3] MTXD[2] MTXD[1] MTXD[0] MTXER MTXCLK MRXDV MRXD[3] MRXD[2] MRXD[1] MRXD[0] VDD_IO GND MRXCLK MCOL MCRS MCOLIN MIIS[1] MIIS[0] Type(Note 1) I I GND Pwr GND P I I I I I I I I I I Pwr GND I I I I I I I/O O O O O O Pwr GND I/O O I/O I I I 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 3 3 2 1 2 1 1 3 2 2 3 3 Port Pin Function Factory test pin Factory test pin Ground for clock recovery circuitry 2.5V for clock recovery circuitry Ground for clock recovery circuitry 2.5V for clock recovery circuitry DIScard VLAN Mismatch packets Force flow control on port 2 Port 3 VLAN Port mask bit 1 Port 3 VLAN Port mask bit 0 Port 2 VLAN Port mask bit 2 Force flow control on port 1 Port 2 VLAN Port mask bit 0 Port 1 VLAN Port mask bit 2 Port 1 VLAN Port mask bit 1 Port 3 auto-negotiation disable (pull this down to enable port 3 auto negotiation) 2.5V for core digital circuitry Ground for digital circuitry MII transmit enable MII transmit bit 3 MII transmit bit 2 MII transmit bit 1 MII transmit bit 0 MII transmit error MII output clock MII receive data valid MII receive bit 3 MII receive bit 2 MII receive bit 1 MII receive bit 0 2.5V or 3.3V for MII interface, LEDs and other digital I/O Ground for digital circuitry MII input clock MII collision detect output MII carrier sense MII collision detect input MII mode select bit 1 MII mode select bit 0
Pwr = power supply GND = ground I = input O = output I/O = bi-directional
May 2005
7
KS8993
KS8993
Pin Number 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115
Note 1.
Micrel
Pin Name MODESEL[3] MODESEL[2] MODESEL[1] MODESEL[0] TESTEN SCANEN RST# VDD GND LED[1][3] LED[1][2] LED[1][1] LED[1][0] LED[2][3] LED[2][2] LED[2][1] LED[2][0] VDD_IO GND LED[3][3] LED[3][2] LED[3][1] LED[3][0] PRSV PRSEL[1] PRSEL[0] PBASE2 PBASE1 PBASE0 P3_1PEN P2_1PEN P1_1PEN P3_TXQ2 P2_TXQ2 P1_TXQ2 GND VDD P3_PP P2_PP Type(Note 1) I I I I I I I Pwr GND O O O O O O O O Pwr GND O O O O I I I I I I I I I I I I GND Pwr I I 3 2 3 2 1 3 2 1 3 3 3 3 1 1 1 1 2 2 2 2 Port Pin Function Selects LED and test modes Selects LED and test modes Selects LED and test modes Selects LED and test modes Factory test pin - tie low for normal operation Factory test pin - tie low for normal operation Reset 2.5V for core digital circuitry Ground for digital circuitry Port 1 LED indicator 3 Port 1 LED indicator 2 Port 1 LED indicator 1 Port 1 LED indicator 0 Port 2 LED indicator 3 Port 2 LED indicator 2 Port 2 LED indicator 1 Port 2 LED indicator 0 2.5V or 3.3V for MII interface, LEDs and other digital I/O Ground for digital circuitry Port 3 LED indicator 3 Port 3 LED indicator 2 Port 3 LED indicator 1 Port 3 LED indicator 0 Priority queue buffer reserve Priority scheme select bit 1 Priority scheme select bit 0 Priority base value bit 2 Priority base value bit 1 Priority base value bit 0 Port 3 802.1p receive priority classification enable Port 2 802.1p receive priority classification enable Port 1 802.1p receive priority classification enable Port 3 transmit queue split, priority queueing enable Port 2 transmit queue split, priority queueing enable Port 1 transmit queue split, priority queueing enable Ground for digital circuitry 2.5V for core digital circuitry Port 3 receive port based priority classification Port 2 receive port based priority classification
Pwr = power supply GND = ground I = input O = output I/O = bi-directional
KS8993
8
May 2005
KS8993
Pin Number 116 117 118 119 120 121 122 123 124 125 126 127 128
Note 1.
Micrel
Pin Name P1_PP P1_TAGINS P2_TAGINS P3_TAGINS P3_TAGRM P2_TAGRM P1_TAGRM VDD_RCV[1] GND_RCV[1] X2 X1 FXSD[1] AOUT Type(Note 1) I I I I I I I Pwr GND O I I O 1 Port 1 1 2 3 3 2 1 1 1 Pin Function Port 1 receive port based priority classification Port 1 tag insertion enable Port 2 tag insertion enable Port 3 tag insertion enable Port 3 tag removal enable Port 2 tag removal enable Port 1 tag removal enable 2.5V for clock recovery circuitry Ground for clock recovery circuitry Connect to crystal input Crystal or clock input Fiber signal detect Factory test output
Pwr = power supply GND = ground I = input O = output I/O = bi-directional
I/O Grouping
Group Name PHY MII SNI IND UP CTRL TEST PWR Description Physical Interface Media Independant Interface Serial Network Interface LED Indicators Unmanaged Programmable Control and Miscellaneous Test (Factory) Power and Ground
May 2005
9
KS8993
KS8993
Micrel
I/O Descriptions
Group PHY I/O Names RXP[1:3] RXM[1:3] TXP[1:3] TXM[1:3] FXSD[1:3] VREF[1:3] ISET Active Status Analog Analog H Analog Analog Description Differential inputs (receive) for connection to media (transformer or fiber module). Differential outputs (transmit) for connection to media (transformer or fiber module). Fiber signal detect - connect to fiber signal detect output on fiber module. Tie low for 100TX mode. Center tap transformer reference for transmit data. Transmit Current Set. Connecting an external reference resistor to set transmitter output current. This pin connects a 1% 3k resistor if a transformer of turns ratio of 1:1 is used. See "Table 2, MII Interconnect" for forward and reverse signal usage. MRXD[0:3] MRXDV MCRS MCOL MCOLIN MRXCLK MTXD[0:3] MTXEN MTXER MTXCLK SNI MTXD[0] MTXEN MTXCLK MRXD[0] MRXDV MCOL MRXCLK IND LED[1:3][0] H H H H H Clock H H H Clock H H Clock H H H Clock L Four bit wide data bus for receiving MAC frames. Receive data valid. Receive carrier sense. Receive collision detection. Collision in (for forward operation only). Receive clock. Four bit wide data bus for transmitting MAC frames. Transmit enable. Transmit error. Transmit clock. Serial transmit data. Transmit enable. Transmit clock. Serial receive data. Receive carrier sense/data valid. Collision detection. Receive clock. Output (after reset). Mode 0: Speed (low = 100/high = 10). Mode 1: Reserved. Mode 2: Collision (toggle = collision during receiving , high = no collision). Mode 3: Speed (low = 100/high = 10). Output (after reset). Mode 0: Duplex (low = full/high = half). Mode 1: Duplex (low = full/high = half). Mode 2: Duplex (low = full/high = half). Mode 3: Reserved. Output (after reset). Mode 0: Collision (toggle = collision during receiving , high = no collision). Mode 1: Transmit Activity (toggle during transmission, high = idle). Mode 2: 10/link/act (constant low = link, toggle = act, constant high = no link). Mode 3: Full-Duplex + Collision (constant low = full-duplex, toggle = collision in half. duplex, constant high = half-duplex with no collision).
MII
LED[1:3][1]
L
LED[1:3][2]
L
KS8993
10
May 2005
KS8993
Group I/O Names LED[1:3][3] Active Status L Description Output (after reset). Mode 0: Link + Activity (toggle = receiving or transmitting, constant low = link, constant high = no link). Mode 1: Receive Activity (toggle during receiving / high = no receiving activity). Mode 2: 100/link/act (constant low = link, toggle = act, constant high = no link). Mode 3: Mode 3: Link + Activity (toggle = receiving or transmitting, constant low = link, constant high = no link).
Micrel
Note: Mode is set by MODESEL[3:0] ; please see description in UP "Unmanaged Programming" section.
UP MODESEL[3:0] H Mode select at reset time. LED mode is selected by using the table below. MODESEL also controls the maximum frame length accepted. MODESEL 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FFLOW1# L 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LED mode LED mode 0 LED mode 1 LED mode 2 LED mode 3 Factory testing Factory testing Factory testing Factory testing Factory testing Factory testing Factory testing LED mode 3 LED mode 0 Factory testing LED mode 2 Factory testing Max Length (no tag/tag) 1518/1522 1518/1522 1518/1522 1518/1522 Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable 1536/1536 1536/1536 Not applicable 1536 / 1536 Not applicable
Enable force flow control feature on port 1. Pulled up = no force flow control feature on port 1 (default). Flow control feature is enabled and disabled by auto-negotiation. Pulled down = enable force flow control feature on port 1 regardless of auto-negotiation result. Program force flow control feature on port 2. Pulled up = no force flow control feature on port 2 (default). Flow control feature is enabled and disabled by auto-negotiation. Pulled down = enable force flow control feature on port 2 regardless of auto-negotiation result. Program advertise flow control feature for 10/100BaseTX ports during auto-negotiation at reset time. Pulled low = no advertise flow control during auto-negotiation. Pulled high = advertise flow control during auto-negotiation (default). Programs force flow control feature on port 3, incuding MII port at reset time. Pulled low = no force flow control feature on port 3, including MII port (default). Flow control feature is enabled/disabled by auto-negotiation result. Pulled high = enable force flow control feature on port 3, including MII port regardless of auto-negotiation result. Reserved - use float configuration.
FFLOW2#
L
LED[1][3]
LED[1][2]
LED[1][1]
May 2005
11
KS8993
KS8993
Group I/O Names LED[1][0] Active Status Description
Micrel
Programs buffer allocation per port at reset time. Use the following table to select the option. Pulled low = 170 buffers (default). Pulled high = adaptive mode. Programs MAC address aging in the address look-up table at reset time. Aging eliminates old entries from the table. Pulled high = 5 minute aging (default). Pulled low = disable. Programs back pressure enable at reset time. Pulled high = enable (default). Pulled low = disable. Programs aggressive back off in half-duplex at reset time. Pulled high = enable (default). Pulled low = disable. Programs no excessive collision drop at reset time. Pulled high = enable (default). Pulled low = disable. RESERVED. Use external pulldown resistor if VDD_IO is 3.3V and LED[3][3] is being used. If VDD_IO is not 3.3V or this LED is not used, then no pull-down is required ( floating). Programs force 100BaseTX mode at reset time. Use the table below to set this mode on the appropriate port. Assuming the corresponding port auto-negotiation is disabled. Signal LED[3][2] LED[3][1] LED[3][0] Port 3 2 1 Force 10BaseTX Pulled low Pulled low Pulled low Force 100BaseTX Pulled high (default) Pulled high (default) Pulled high (default)
LED[2][3]
LED[2][2]
LED[2][1]
LED[2][0]
LED[3][3]
LED[3][2:0]
MRXD[3:1]
Programs force full-duplex mode at reset time. Use the table below to set this mode on the appropriate port. Assuming the corresponding port auto-negotiation is disabled. Signal MRXD[3] MRXD[2] MRXD[1] Port 3 2 1 Force Half-Duplex Pulled low (default) Pulled low (default) Pulled low (default) Force Full-Duplex Pulled high Pulled high Pulled high
MRXD0
Programs "port 1 auto-negotiation disable" at reset time. Pulled high = auto-negotiation disable. Pulled low = auto-negotiation enable (default). Programs "port 2 auto-negotiation disable" at reset time. Pulled high = auto-negotiation disable. Pulled low = auto-negotiation enable (default). Programs "port 3 auto-negotiation disable" at reset time. Pulled high = auto-negotiation disable (default) Pulled low = auto-negotiation enable H Selects external MII port operation mode. Use the table below to select the external port mode. MIIS 1 L L H H 0 L H L H Selection External MII disable (default) MII reverse mode MII forward mode 7-wire (SNI) mode
MCOL
DISAN3
MIIS[1:0]
KS8993
12
May 2005
KS8993
Group I/O Names VMDIS Active Status H Description VLAN Mismatch Discard control. Pulled low = Constrict multicast and broadcast packets to VLAN. Pulled high = Constrict all packets to VLAN (default). Reserve priority buffers. Pulled low = No buffers reserved (default). Pulled high = Reserve 96 buffers per port for high priority queue.
Micrel
PRSV
H
PBASE[2:0]
H
Priority base value used to compare with priority tag in 802.1p tag. When a packet is received that has a 802.1p tag and 802.1p processing is enabled (Px_1PEN=H), the PBASE value is compared to the tag priority field. If the packet tag is greater than or equal to the PBASE value, the packet is sent to the higher priority transmit queue while tags less than PBASE are sent to the lower priority queue. (default = 100). VLAN mask bits. Used to select which ports are seen from any particular port. Use the table below to select VLAN operation. P1_V defined as (PV13, PV12, 1) P2_V defined as (PV23, 1 , PV21) P3_V defined as (1 , PV32, PV31) P[3:1]_V Port 1
PV12 PV13 PV21 PV23 PV31 PV32
H
2 0 1 1 0 1 1 1 1 1
1 1 0 1 1 1 1 0 1 1
0 1 1 1 1 0 1 1 0 1
VLAN State Ports 1 and 2 in VLAN Ports 1 and 3 in VLAN Ports 1, 2 and 3 in VLAN (default) Ports 1 and 2 in VLAN Ports 2 and 3 in VLAN Ports 1, 2 and 3 in VLAN (default) Ports 1 and 3 in VLAN Ports 2 and 3 in VLAN Ports 1, 2 and 3 in VLAN (default)
2
3
Note that a minimum of 2 ports are required for each VLAN. The VLAN configuration is viewed from the receiver perspective. All states not listed above are invalid.
P[3:1]_1PEN H Enables 802.1p prioritizing on a per port basis. The enable is from the receive perspective. If the 802.1p processing is disabled or there is no tag, priority is detemined by the P[3:1]_PP bit. Pulled low = Disable 802.1p prioritizing (default). Pulled high = Enable 802.1p prioritizing. Selects port receive priority in the absence of 802.1p handling. Pulled low = Low priority (default). Pulled high = High priority. Inserts 802.1p tag in received packets if not already existent. The priority field is set based on the port P[3:1]_PP bit. For the P[3:1]_PP bit tied low, the priority field is set to 000 and for the P[3:1]_PP bit tied high, the priority field is set to 111. Pulled low = No change to received packet (default). Pulled high = Insert 802.1p tag.
P[3:1]_PP
H
P[3:1]_TAGINS
H
Note that if P[3:1]_TAGINS and P[3:1]_TAGRM are both set for the same port, there is no change to the packet.
P[3:1]_TAGRM H Removes 802.1p tag in received packets if they exist. Pulled low = No change to received packet (default). Pulled high = Remove 802.1p tag.
Note that if P[3:1]_TAGINS and P[3:1]_TAGRM are both set for the same port, there is no change to the packet.
P[3:1]_TXQ2 H Selects transmit queue split on a per port basis. The split sets up high and low priority queues. Pulled low = Single transmit queue (default) Pulled high = Separate high and low transmit queues
May 2005
13
KS8993
KS8993
Group I/O Names PRSEL[1:0] Active Status H Description
Micrel
Selects queue servicing if using split transmit queues. Use the table below to select desired servicing. Note that this selection effects all split transmit queue ports in the same way. PRSEL 1 0 L L H H L H L H Priority Selection Transmit all high priority before low priority (default) Transmit high priority at 10:1 ratio Transmit high priority at 5:1 ratio Transmit high priority at 2:1 ratio
CTRL
X1 X2 RST#
Clock Clock L H H H H
External crystal or clock input Used when other polarity of crystal is needed. This is unused for a normal clock input. System reset Factory test input - pull low Factory test input - pull low Factory test output - leave open Mux[1] Float 1 0 Float Mux[2] Float Float Float 1 Default for factory test purpose TX Disable Port 1 TX Disable Port 2 Power Down Port 3
TEST
TESTEN SCANEN AOUT MUX[1:2]
Special note: all other combinations are not allowed
TEST[1:2] H Test[1] Float Float Test[2] Float 0 Default for factory test purpose Far End Fault Disable
Special note: all other combinations are not allowed .
PWR VDD_RX[1:3] GND_RX[1:3] VDD_TX[1:3] GND_TX[1:3] VDD_RCV[1:3] GND_RCV[1:3] VDD_PLL GND_PLL GND_ANA GND_BG VDD_BG VDD VDD_IO GND 2.5V for receiver Ground for receiver 2.5V for transmit circuitry Ground for transmit circuitry 2.5V for clock recovery circuitry Ground for clock recovery 2.5V for phase locked loop circuitry Ground for phase locked loop circuitry Analog ground Analog ground 2.5V for analog circuits 2.5V for core digital circuitry 2.5V or 3.3V for MII interface, LEDs and other digital I/O Ground for digital circuitry
KS8993
14
May 2005
KS8993
May 2005
PBASE2 PBASE1 PBASE0 P3_1PEN P2_1PEN P1_1PEN P3_TXQ2 P2_TXQ2 P1_TXQ2 GND VDD P3_PP P2_PP P1_PP P1_TAGINS P2_TAGINS P3_TAGINS P3_TAGRM P2_TAGRM P1_TAGRM VDD_RCV[1] GND_RCV[1] X2 X1 FXSD[1] AOUT
103 1
Pin Configuration
128-Pin PQFP (PQ)
15
39
65
GND_ANA MUX[2] MUX[1] GND_RX[1] RXP[1] RXM[1] VDD_RX[1] VREF[1] TXP[1] TXM[1] GND_TX[1] VDD_TX[1] VDD_BG ISET GND_BG GND_PLL VDD_PLL GND_RX[2] RXP[2] RXM[2] VDD_RX[2] VREF[2] TXP[2] TXM[2] GND_TX[2] VDD_TX[2] VDD_TX[3] VDD_TX[3] TXP[3] TXM[3] VREF[3] VDD_RX[3] RXP[3] RXM[3] GND_RX[3] FXSD[2] FXSD[3] GND_ANA
PRSEL[0] PRSEL[1] PRSV LED[3][0] LED[3][1] LED[3][2] LED[3][3] GND VDD_IO LED[2][0] LED[2][1] LED[2][2] LED[2][3] LED[1][0] LED[1][1] LED[1][2] LED[1][3] GND VDD RST# SCANEN TESTEN MODESEL[0] MODESEL[1] MODESEL[2] MODESEL[3] MIIS[0] MIIS[1] MCOLIN MCRS MCOL MRXCLK GND VDD_IO MRXD[0] MRXD[1] MRXD[2] MRXD[3]
MRXDV MTXCLK MTXER MTXD[0] MTXD[1] MTXD[2] MTXD[3] MTXEN GND VDD DISAN3 PV12 PV13 PV21 FFLOW1# PV23 PV31 PV32 FFLOW2# VMDIS VDD_RCV[3] GND_RCV[3] VDD_RCV[2] GND_RCV[2] TEST[2] TEST[1]
KS8993
Micrel
KS8993
Micrel
Functional Overview: Physical Layer Transceiver
100BaseTX Transmit
The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ to NRZI format, then transmitted in MLT3 current output. The output current is set by an external 1% 3.01k resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies to the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitters.
100BaseTX Receive
The 100BaseTX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial to parallel conversion. The receiving side starts with the equalization filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against the environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is provided as the input data to the MAC.
PLL Clock Synthesizer
The KS8993 generates clocks for the external MII and SNI interface based on the interface type selected.
Scrambler/De-scrambler (100BaseTX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled by the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter.
100BaseFX Operation
100BaseFX operation is very similar to 100BaseTX operation with the differences being that the scrambler/de-scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation.
100BaseFX Signal Detection
The physical port runs in 100BaseFX mode if FXSDx >.6V. This signal is referenced to VREFx which is set at 1/2 Vdd but can be overridden by an external level. VREFx can be connected to the "minus" signal of a differential pair coming from the fiber module ("plus connects to FXSDx) used to convey signal detect. When FXSDx is below .6V then 100BaseFX mode is disabled.
100BaseFX Far End Fault
Far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, the transmission side signals the other end of the link by sending 84 1's followed by a zero in the idle period between frames. Far End Fault can be disabled by setting external hardware pin TEST[2]=0 and TEST[1] = float. See "I/O Description" for pin description.
10BaseT Transmit
The output 10BaseT driver is incorporated into the 100BaseT driver to allow transmission with the same magnetic. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.2V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. Special note for 10BaseT operation: With an operating voltage of 2.5V, the KS8993 does not always achieve the specified transmit voltage swing greater than or equal to 2.2V as specified by IEEE 802.3. The important factor however is that the KS8993 does adhere to the specified receive signal voltages using the IEEE twisted pair model with a 100 load. The transmit voltage swing can be increased to 2.2V or above by increasing the supply voltage to 2.65V if so desired.
10BaseT Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A KS8993 16 May 2005
KS8993
Micrel
squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8993 decodes a data frame. The receiver clock is maintained active during idle periods in between data reception.
Power Management
Power Save Mode
The KS8993 will turn off everything except for the Energy Detect and PLL circuits when the cable is not installed on an individual port basis. In other words, the KS8993 will shutdown most of the internal circuits to save power if there is no link. An additional features are available: Transmit Disable for Port 1 set external pin MUX[1] = 1 and MUX[2] = Float Transmit Disable for Port 2 set external pin MUX[1] = 0 and MUX[2] = Float Power Down on Port 3 set external pin MUX[1] = float and MUX[2] = 1 See "I/O Description" section for pin description.
LED Mode Selection
Use the following table as a quick reference for setting the LED mode. See MODESEL "I/O Description" section for MODESEL[3:2] usage.
MODESEL[1:0] 00 01 10 11 LED[1:3]3 Link + Act RX Act 100 / Link / Act Link + Act LED[1:3]2 Collision TX Act 10 / Link / Act FDX + Collision LED[1:3]1 FDX FDX FDX Reserved LED[1:3]0 Speed Reserved Collision Speed
Table 1. LED Mode Selection
Auto-Negotiation
The KS8993 conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the best common mode of operation. In auto-negotiation the link partners advertise capabilities across the link to each other. If auto-negotiation is not supported or the link partner to the KS8993 is forced to bypass auto-negotiation, then the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto-negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. The flow for the link set up is depicted below.
Start Auto-Negotiation
Force Link Setting
No
Parallel Operation
Yes
Bypass Auto-Negotiation and Set Link Mode
Attempt Auto-Negotiation
Listen for 100BaseTX Idles
Listen for 10BaseT Link Pulses No
Join Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 2. Auto-Negotiation May 2005 17 KS8993
KS8993
Micrel
Functional Overview: Switch Core
Address Look-Up
The internal look-up table stores MAC addresses and their associated information. It contains 1K full CAM with 48-bit address plus switching information. The KS8993 is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn.
Learning
The internal look-up engine will update its table with a new entry if the following conditions are met: * The received packet's SA does not exist in the look-up table. * The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will insert the qualified SA into the table, along with the port number, time stamp. If the table is full, the last entry of the table will be deleted first to make room for the new entry.
Migration
The internal look-up engine also monitors whether a station is moved. If it happens, it will update the table accordingly. Migration happens when the following conditions are met: * The received packet's SA is in the table but the associated source port information is different. * The received packet is good; the packet has no receiving errors, and is of legal length. The look-up engine will update the existing record in the table with the new source port information.
Aging
The look-up engine will update time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will then remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is approximately 300 seconds 75 sec. This feature can be enabled or disabled by external pull-up or pull-down resistors. If aging is disabled and look-up table is full, KS8993 will remove the largest address in the table which has been sorted by the binary search.
Forwarding
The KS8993 will forward packets as follows: * If the DA look-up results is a "match", the KS8993 will use the destination port information to determine where the packet goes. * If the DA look-up result is a "miss", the KS8993 will forward the packet to all other ports except the port that received the packet. * All the multicast and broadcast packets will be forwarded to all other ports except the source port. The KS8993 will not forward the following packets: * Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. * 802.3x pause frames. The KS8993 will intercept these packets and do the appropriate actions. * "Local" packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches the port where the packet was from, the packet is defined as "local".
Switching Engine
The KS8993 has a very high performance switching engine to move data to and from the MAC's, packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KS8993 has an internal buffer for frames that is 16kx32 (64kB). This resource is shared between the three ports. Buffer sizing per port can be programmed at system reset time by using the unmanaged program mode (I/O strapping). Each buffer is sized at 128B and therefore there are a total of 512 buffers available. A per port maximum can be set at 170 buffers (equal allocation). There is also an adaptive mode that reacts to port traffic. In the adaptive mode any given port may use up to 256 buffers provided that the other ports are lightly loaded. In the event of heavier loading on other ports the limit is 170 buffers.
MAC (Media Access Controller) Operation
The KS8993 strictly abides by IEEE 802.3 standard to maximize compatibility and interoperability with other vendors.
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96 bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96 bit time IPG is measured from MCRS and the next MTXEN. KS8993 18 May 2005
KS8993
Back off Algorithm
Micrel
The KS8993 implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional "aggressive mode" back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration.
Late Collision
If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped.
Illegal Frames
The KS8993 will discard illegal size frames defined by the IEEE Std 802.3u, including short frames (less than 64 bytes), long frames (greater than 1522 bytes), and FCS error frames. The KS8993 treats VLAN tagged frames as regular frames and does not perform any VLAN related functions. Switches built with the KS8993's should be treated as a single VLAN domain. KS8993 will drop VLAN frames if the size is larger than 1522 bytes and drop non-VLAN frames if the size is larger than 1518 bytes. Note that in a special mode, frame lengths of up to 1536 bytes are accepted. This is controlled by MODESEL[3:0]. See "I/O Descriptions" section for more details.
Flow Control
KS8993 supports standard 802.3x flow control frames for full-duplex mode and back-pressure for half-duplex.
Full-Duplex Flow Control (IEEE 802.3x standard)
The flow control capabilities of the KS8993 are enabled based upon the results of the auto-negotiation. During the autonegotiation, 10/100BaseTX port of KS8993 will advertise this feature to the Link Partner. KS8993 will only establish flow control if the Link Partner has the flow control capability. Since 100BaseFX does not support auto-negotiation, 100BaseFX port will not advertise flow control to the Link Partner. On the receive side, if the KS8993 receives a pause control frame, the KS8993 will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KS8993 will be transmitted. On the transmit side, the KS8993 has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KS8993 will flow control a port, which just received a packet, if the destination port resource is being used up. The KS8993 will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KS8993 will send out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysterisis feature is provided to prevent flow control mechanism from being activated and deactivated too many times. The KS8993 will flow control all ports if the receive queue becomes full. Take a special note that flow control for 100BaseFX or 10/100BaseTX full-duplex can be forced regardless of auto-negotiation result. This force flow control feature on port 1, 2 or 3 can be enabled and disabled via external pin FFLOW#1, FFLOW#2 and LED[1][2] respectively.
Half-Duplex Back Pressure
Half-duplex Back Pressure option (Note: not in 802.3 standards) is also provided. The activation and deactivation conditions are the same as the above in full-duplex mode. If back pressure is required, the KS8993 will send preambles to defer other stations' transmission (carrier sense deference). To avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier sense type back pressure will be interrupted and those packets will be transmitted instead. If there are no more packets to send, carrier sense type back pressure will be active again until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. This scheme is better than collision based back pressure.
VLAN Support
Each port is associated with a 3-bit Port VLAN mask register (PV) (P1_V: (PV13, PV12, 1), P2_V: (PV23, 1, PV21), P3_V: (1, PV32, PV31)). Based on the receiving port's PV, a broadcast packet will be sent to all the ports that have their mask bit set to one, excluding the source port. In other words, broadcast packets will be confined in the VLAN specified in the PV. A unicast packet, which is destined to a port not specified in the PV, could be optionally filtered (depends on the strapped in value during power up, VLAN Mismatch DIScard). The following is a typical set up for a router/switch combo application, in which port 3 is a router port:
May 2005
19
KS8993
KS8993
Micrel
P1_V : (1,0,1) P2_V : (1,1,0) P3_V : (1,1,1) In the above setting, there are two VLANs. VLAN 1 includes ports 1,3 and VLAN 2 includes ports 2, 3. Port 3 belongs to both VLANs. If vmdis = 1, port 1 can never talk to port 2. Port 3 has to route all the traffic across the two VLANs. If vmdis = 0 and there are unicast packets, all ports can talk to all others. If vmdis = 0 and there are multicast packets, those packets are confined in the same VLAN. The router can take advantage of the "vmdis = 0" feature, acting as an agent to handle broadcast/multicast protocol, while leaving unicast switching task to KS8993. For example, port 1 sends an "ARP" for the port 2 MAC address. Since port 2 cannot receive the ARP, the attached router on port 3 will act as an agent and report the MAC address of port 2 to port 1. Then all the unicast traffic between port 1 and port 2 could be switched by KS8993, instead of by the router port. This application could enable "wire speed" switching/routing. This feature is sometimes called "leaky VLAN". This leaky VLAN does improve the system performance by separating broadcast domains. Note KS8993 does not support "duplicated MAC addresses" in different VLANs to save MAC table size.
QoS Priority Support
This feature provides QoS for applications such as VOIP, video conferencing, and mission critical applications. The KS8993 per port transmit queue could be split into two priority queues, high priority and low priority queues. The splitting feature could be optionally per port enabled (using pin Px_TXQ2). If a port is split, high priority packets will be put in the high priority queue. If a port's transmit queue is not split, high priority and low priority packets will be treated equally. There are four priority schemes (selected by pins PRSEL1 and PRSEL0): (1), transmit high priority packets always before low priority packets, i.e. A low priority packet could be transmitted only when the high priority queue is empty. (2), 10/1 ratio, transmit a low priority after every 10 high priority packets transmitted if both queues are busy. (3), 5/1 ratio, (4) 2/1 ratio. Incoming packet priority could be classified in two ways, port-based or 802.1p.
Port based priority: Each port could be individually specified as a high priority receiving port (using pin Px_PP). All the packets received at the high priority receiving port will be marked high priority and sent to the high priority transmit queue if the corresponding queue is split. 802.1p based priority: 802.1p based priority could be enabled by pins Px_1PEN. KS8993 will examine incoming packets to determine whether they are tagged and retrieve the corresponding priority information. The priority field in the VLAN tag is 3 bits wide and is compared against "priority base value specified by pins (PBASE[2:0]). If a received packet has an equal or larger priority value than the "priority base" value, the packet will be put in the high priority transmit queue if the corresponding queue is split. KS8993 can optionally remove or insert priority tagged frame's header (2 bytes of tag protocol identifier 0x8100 and 2 bytes of tag control information). If a transmitting port has its corresponding Px_TAGINS set (meaning tag insertion), the transmitting logic will automatically insert "priority tag" for untagged packets with NULL VLAN ID and its priority value (7 for high priority and 0 for low priority). For already tagged packets, KS8993 will pass the original packet without changing its tag content. If a transmitting port has its corresponding Px_TAGRM set (meaning tag removal), the transmitting logic will automatically remove "802.1q tag". For untagged packets, KS8993 will pass the original packet without changing any content. Either tag insertion or removal will cause CRC recalculation.
KS8993
20
May 2005
KS8993
Micrel
MII Interface Operation
The MII (Media Independent Interface) operates in either a forward or reverse mode. In the forward mode, the KS8993 MII acts like a MAC and in the reverse mode, it acts like a PHY device. This interface is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. There are two distinct groups, one being for transmission and the other for receiving. The table below describes the signals used in this interface in forward and reverse modes. This interface is a nibble wide data interface and therefore runs at 1/4 the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicates a collision has occurred during transmission. Note that the signal MRXER is not provided on the MII interface for the KS8993 for reverse operation and MTXER is not represented for forward mode. Normally this would indicate a receive / transmit error coming from the physical layer /MAC device, but is not appropriate for this configuration. If the connecting device has a MRXER pin, this should be tied low on the other device for reverse or if it has a MTXER pin in the forward mode it should also be tied low on the other device.
Reverse MII Mode Connection
External MAC MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8993 Signal MTXEN MTXER MTXD[3] MTXD[2] MTXD[1] MTXD[0] MTXCLK MCOL MCRS MRXDV Not used MRXD[3] MRXD[2] MRXD[1] MRXD[0] MRXCLK Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock
Forward MII Mode Connection
External PHY MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8993 Signal MRXDV Not used MRXD[3] MRXD[2] MRXD[1] MRXD[0] MTXCLK MCOLIN MCRS MTXEN MTXER MTXD[3] MTXD[2] MTXD[1] MTXD[0] MRXCLK
Table 2. MII Interconnect
May 2005
21
KS8993
KS8993
Micrel
SNI Interface (7-wire) Operation
The SNI (Serial Network Interface) is intended to interface with some controllers used for network layer protocol processing. KS8993 acts like a PHY device to external controllers. This interface can be directly connected to these type of devices. The signals are divided into two groups, one being for transmission and the other being the receive side. The signals involved are described in the table below. This interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid. For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
SNI Signal TXEN TXD TXC COL CRS RXD RXC
Description Transmit enable Serial transmit data Transmit clock Collision detection Carrier sense Serial receive data Receive clock
KS8993 SNI Signal MTXEN MTXD[0] MTXCLK MCOL MRXDV MRXD[0] MRXCLK
KS8993 Input/Output Input Input Output Output Output Output Output
Table 3. SNI Signal
KS8993
22
May 2005
KS8993
Micrel
Absolute Maximum Ratings (Note 1)
Supply Voltage (VDD_RX, VDD_TX, VDD_BG, VDD_PLL, VDD_RCV, VDD) ........................................ -0.5V to +3.0V (VDD_IO) ................................................... -0.5V to +4.0V Input Voltage (All Inputs) ............................. -0.5V to +4.0V Output Voltage (All Outputs) ....................... -0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270C Storage Temperature (TS) ....................... -55C to +150C
Operating Ratings (Note 2)
Supply Voltage (VDD_RX, VDD_TX, VDD_BG, VDD_PLL, VDD_RCV, VDD) .................................... +2.35V to +2.75V (VDD_IO) .................. +2.35V to +2.75V or +3.0V to +3.6V Ambient Temperature (TA) ........................... -0C to +70C Package Thermal Resistance (Note 3) PQFP (JA) No Air Flow ................................. 42.91C/W
Electrical Characteristics (Note 4)
VDD = 2.5V to 2.75V; TA = 0C to +70C; unless noted, bold values indicate -40C TA +85C; unless noted. Symbol Parameter Condition Min Typ Max Units Total Supply Current (including TX output driver current) IDD1 IDD2 VIH VIL VOH VOL Normal 100BaseTX Normal 10BaseT 300 200 330 230 mA mA
TTL Inputs (VDDIO = 3.3V or 2.5V) Input High Voltage Input Low Voltage VDD (I/O) -0.8 0.8 V V
TTL Outputs (VDDIO = 3.3V or 2.5V) Output High Voltage Output Low Voltage IOH = -4mA IOL = 4mA VDD (I/O) -0.4 0.4 V V
100BaseTX Receive Error Rate 100BaseTX Transmit (measured differentially after 1:1 transformer) VO VIMB tr, tt VSET Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time 50 from each output to VDD 50 from each output to VDD 3 0.95 1.5 5 1.05 V % ns 1.0 1E-8
100BaseTX Transmit (measured differentially after 1:1 transformer) Reference Voltage of ISET Output Jitters Peak-to-peak 0.75 0.7 1.4 ns ns
10BaseTX Transmit (measured differentially after 1:1 transformer) Near End Normal Link Pulse Far End Normal Link Pulse Far End Output Jitters
Note 1. Note 2. Note 3. Note 4.
VDD = 2.6V After 100 meters Cat-3 cable After 100 meters Cat-3 cable
2.2 0.5 -8 8
V V ns
Exceeding the absolute maximum rating may damage the device. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD). No HS (heat spreader) in package. Specification for packaged product only.
May 2005
23
KS8993
KS8993
Micrel
Timing Diagrams
tcyc MTXCLK
ts MTXD[0], MTXEN
th
Figure 3. SNI (7-Wire) Input Timing
Symbol tCYC tS tH
Parameter Clock Cycle Set-Up Time Hold Time
Min
Typ 100
Max
Units ns ns ns
10 0
Table 4. SNI (7-Wire) Input Timing Parameters
tcyc MRXCLK tov
MRXD[0], MRXDV, MCOL
Figure 4. SNI (7-Wire) Output Timing
Symbol tCYC tOV
Parameter Clock Cycle Output Valid
Min
Typ 100
Max
Units ns
0
3
6
ns
Table 5. SNI (7-Wire) Output Timing Parameters
KS8993
24
May 2005
KS8993
Micrel
MTXCLK
Uplink Module MAC
MTXD[3:0]
MTXEN
KS8993's Port 3 Acting Like a PHY
MTXER
tcyc MTXCLK
ts MTXD[3:0] MTXEN MTXER
th
Figure 5. Reverse MII Timing-Receive Data from MII
Symbol tCYC tS tH
Parameter Clock Cycle Set-Up Time Hold Time (100BaseT) (10BaseT)
Min
Typ 40 400
Max
Units ns ns ns
10 0
Table 6. Reverse MII Timing-Receive Data from MII Parameters
May 2005
25
KS8993
KS8993
Micrel
MRXCLK
Uplink Module MAC
MRXD[3:0]
MRXDV
KS8993's Port 3 Acting Like a PHY
tcyc MRXCLK tov
MRXD[3:0] MRXDV
Figure 6. Reverse MII Timing-Transmit Data to MII
Symbol tCYC tOV
Parameter Clock Cycle Output Valid (100BaseT) (10BaseT)
Min
Typ 40 400
Max
Units ns
18
25
28
ns
Table 7. Reverse MII Timing-Transmit Data to MII Parameters
KS8993
26
May 2005
KS8993
Micrel
MRXCLK
KS8993's Port 3 Acting Like a MAC
MTXD[3:0]
External PHY
MTXEN MTXER
tcyc MRXCLK
ts MTXD[3:0] MTXEN MTXER
th
Figure 7. Forward MII Timing-Receive Data from MII
Symbol tCYC tS tH
Parameter Clock Cycle Set-Up Time Hold Time (100BaseT) (10BaseT)
Min
Typ 40 400
Max
Units ns ns ns ns
10 5
Table 8. Forward MII Timing-Receive Data from MII Parameters
May 2005
27
KS8993
KS8993
Micrel
MTXCLK
KS8993's Port 3 Acting Like a MAC
MRXD[3:0]
External PHY
MRXDV
tcyc MTXCLK tov
MRXD[3:0] MRXDV
Figure 8. Forward MII Timing-Transmit Data to MII
Symbol tCYC tOV
Parameter Clock Cycle Output Valid (100BaseT) (10BaseT)
Min
Typ 40 400
Max
Units ns ns
7
11
16
ns
Table 9. Forward MII Timing-Transmit Data to MII
KS8993
28
May 2005
KS8993
Micrel
Reference Circuit
See "I/O Description" section for pull-up/pull-down and float information.
2.5 V
Pull-Up 10k
LED pin
220
KS8993
2.5 V
Float
220
LED pin
KS8993
2.5 V
Pull Down Pull-down 220
LED pin
KS8993 1k
Reference circuits for unmanaged programming through LED ports
Reset Circuit Diagram
Micrel recommendeds the following discrete reset circuit as shown in Figure 9 when powering up the KS8993 device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 10.
VCC
D1 KS8993 RST C 10F
R 10k
CPU/FPGA RST_OUT_n D2
D1, D2: 1N4148
Figure 9. Recommended Reset Circuit.
May 2005
29
KS8993
KS8993
VCC D1: 1N4148 D1 KS8993 RST C 10F R 10k
Micrel
Figure 10. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.
KS8993
30
May 2005
KS8993
Micrel
4B/5B Coding
In 100BaseTX and 100BaseFX the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4B/5B code. The extra code space is required to encode extra control (frame delineation) points. It is also used to reduce run length as well as supply sufficient transitions for clock recovery. The table below provides the translation for the 4B/5B coding.
Code Type Data 4B Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Control Not defined 0101 0101 Not defined Not defined Not defined Invalid Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined 5B Code 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Value Data value 0 Data value 1 Data value 2 Data value 3 Data value 4 Data value 5 Data value 6 Data value 7 Data value 8 Data value 9 Data value A Data value B Data value C Data value D Data value E Data value F Idle Start delimiter part 1 Start delimiter part 2 End delimiter part 1 End delimiter part 2 Transmit error Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
Table 10. 4B/5B Coding
May 2005
31
KS8993
KS8993
Micrel
MLT3 Coding
For 100BaseTX operation the NRZI (Non-Return to Zero Invert on ones) signal is line coded as MLT3. The net result of using MLT3 is to reduce the EMI (Electro Magnetic Interference) of the signal over twisted pair media. In NRZI coding, the level changes from high to low or low to high for every "1" bit. For a "0" bit there is no transition. MLT3 line coding transitions through three distinct levels. For every transition of the NRZI signal the MLT3 signal either increments or decrements depending on the current state of the signal. For instance if the MLT3 level is at its lowest point the next two NRZI transitions will change the MLT3 signal initially to the middle level followed by the highest level (second NRZI transition). On the next NRZI change, the MLT3 level will decrease to the middle level. On the following transition of the NRZI signal the MLT3 level will move to the lowest level where the cycle repeats. The diagram below describes the level changes. Note that in the actual 100BaseTX circuit there is a scrambling circuit and that scrambling is not shown in this diagram.
Hex Value Binary 4B Binary 5B
A
3
8
E
9
4
T3
R3
I1
I1
1010 0011 1000 1110 1001 0100 UUUU UUUU UUUU UUUU 10110101011001011100100110101001101001111111111111
NRZ
NRZI
MLT3
Figure 11. MLT3 coding
The MAC (Media Access Control) fields are described in the table below.
Field Preamble/SFD DA SA 802.1p tag Length Protocol/Data Frame CRC ESD Idle Octect Length 8 6 6 4 2 46 to 1500 4 1 Variable Description Preamble and Start of Frame Delimiter 48-bit Destination MAC Address 48-bit Source MAC Address VLAN and priority tag (optional) Frame Length Higher Layer Protocol and Frame Data 32-bit Cyclical Redundancy Check End of Stream Delimiter Inter Frame Idles
Table 11. MAC Frame for 802.3
KS8993
32
May 2005
KS8993
Micrel
802.1q VLAN and 802.1p Priority Frame
The 3-bit of 802.1p priority is embedded into the 802.1q VLAN frame as described below:
6
6
2
VLAN ID
2
Tag Control
2 Type 12
VLAN Identifier
46-1500 Data
4 FCS
DA SA
(bit)
Protocol ID
16
3
802.1P Priority
1
Priority CFI
802.1Q VLAN
Figure 12. 802.1p and 802.1q Frame Format
May 2005
33
KS8993
KS8993
Micrel
Selection of Isolation Transformer(Note 1)
One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics.
Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.)
Note 1.
Value 1 CT : 1 CT 350H 0.4H 12pF 0.9 1.0dB 1500Vrms
Test Condition
100mV, 100 KHz, 8mA 1MHz (min.)
0MHz to 65MHz
The IEEE 802.3u standard for 100BaseTX assumes a transformer loss of 0.5 dB. For the transmit line transformer, insertion loss of up to 1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value.
Selection of Reference Crystal
An oscillator or crystal with the following typical characteristics is recommended.
Characteristics Name Frequency Frequency Tolerance (max.) Value 25.00000 100 Units MHz ppm
The following transformer vendors provide pin-to-pin compatible parts for Micrel's device: Type Vendor Transformer only Pulse YCL Trans-Power Integrated RJ45 and Transformer Trans-Power Quad Part H1060 PH406080 HB826-10 RJG4-754-C-NL Vendor Pulse YCL Trans-Power Trans-Power Single Part H1012 20PMT04 HB614-1-LP RJ754-C-NL
Table 12. Qualified Transformer Lists
KS8993
34
May 2005
KS8993
Micrel
Package Information
128-Pin PQFP (PQ)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
May 2005
35
KS8993

▲Up To Search▲

Price & Availability of KS8993I

	To Download KS8993I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .